The present invention relates to a power semi-conductor device, and more particularly to an injection enhanced insulated gate bipolar transistor (hereinafter called as a "IEGT").
This application is based on Japanese Patent Application No.08-246303, filed Sep. 18, 1996, the content of which is incorporated herein by reference.
A power semiconductor device of a voltage operation type using an insulated gate, such as an EST (Emitter Switched Thyristor) or MCT (MOS Controlled Thyristor), is able to simplify a driver circuit thereof as compared with a current operation type power semiconductor device, such as a GTO (Gate Turn-off Thyristor).
However, the power semiconductor device having the insulated gate of the above-mentioned type has a problem in that the on-state voltage is excessively high. To solve the above-mentioned problem, it is suggested that a buried insulated gate is used.
FIG. 1 is a perspective cross sectional view showing a conventional power semiconductor device using the buried insulated gate.
An n type buffer layer 2, a high impedance n.sup.- type base layer 3 and a p type base layer 4 are sequentially stacked on a high concentration p.sup.+ type emitter layer 1.
A high concentration n.sup.+ type emitter layer 5 is partially formed in the surface region of the p type base layer 4. A plurality of elongated emitter layers 5 extending in one direction (the lateral direction in FIG. 1) are formed. A plurality of trench grooves extending from the n.sup.+ type emitter layer 5 to reach the n.sup.- type base layer 3 through the p type base layer 4 are formed in the surface region of the device on which the n.sup.+ type emitter 5 is formed. The trench grooves are provided being perpendicular to the elongated emitter layers 5 so that trench grooves are extending in the longitudinal direction. A gate electrode 7 is buried in the trench groove through a gate oxide film 6. A cathode electrode 9 is formed on the surfaces of the p type base layer 4 and the n.sup.+ type emitter layer 5 through an insulation film 10. The cathode electrode 9 is connected to the n.sup.+ type emitter layer 5 and the p type base layer 4 through a through hole formed in the insulation film 10. An anode electrode 8 is formed on the overall surface of the p.sup.+ type emitter layer 1 opposite to the n type buffer layer 2.
The depth, width and the intervals of the trench grooves in which the gate electrodes 7 are buried are designed optimally in such a manner that a low on-state voltage equivalent to that of the thyristor can be obtained though the device does not perform the thyristor operation. The optimum design is a design with which the efficiency to inject electrons from the n.sup.+ type emitter layer 5 to the n.sup.- type base layer 3 can be raised and the voltage drop in the MOS portion can be lowered. As a result, the density of carriers accumulated in the n.sup.- type base layer 3 adjacent to the n.sup.+ type emitter layer 5 can be raised so that the low on-state voltage is realized.
Although the power semiconductor device having the buried insulated gate shown in FIG. 1 is able to obtain the on-state voltage lower than that obtainable from a power semiconductor device having an insulated gate formed such that the gate electrode is formed on the surface of the device, the device of the foregoing type has a critical problem in that the gate has lower gate breakdown voltage as compared with the power semi-conductor device of the type having an insulated gate formed such that the gate electrode is formed on the surface of the device.
Although the power semiconductor device having the buried insulated gate shown in FIG. 1 is able to obtain the on-state voltage lower than that obtainable from a power semiconductor device having an insulated gate formed such that the gate electrode is formed on the surface of the device, an expected low on-state voltage obtained by simulation cannot be realized.
Assuming that the depth of the trench grooves in a portion projecting into the n.sup.- type base layer 3 is T (.mu.m) and the length of the half cell is W (.mu.m), the relationship among T, T.multidot.W and the on-state voltage is examined. Although the value of T.multidot.W with which the on-state voltage has the minimum value must not theoretically be changed even if the value of T is changed. However, the value of T.multidot.W is undesirably changed if T is changed. Thus, there arises a problem in that the design of the device cannot easily be performed.